米尔MYD-C7Z020开发板开发（五）膨胀算法实现

stanauo · 发表于 2019-12-20 19:31:12

膨胀是将与物体接触的所有背景点合并到该物体中，使边界向外部扩张的过程。可以用来填补物体中的空洞。用3X3的结构元素，扫描图像的每一个像素，用结构元素与其覆盖的二值图像做“与”操作，如果都为0，结果图像的该像素为0,。否则为1。结果：使二值图像扩大一圈。

先腐蚀后膨胀的过程称为开运算。用来消除小物体、在纤细点处分离物体、平滑较大物体的边界的同时并不明显的改变其面积。先膨胀后腐蚀的过程称为比运算，用来填充物体内细小空间、连接邻近物体、平滑其边界的同时并不明显改变其面积。

算法的实现，可以用下式子来表示，即3x3像素的运算：

P = P11 || P12 || P13 || P21 || P22 || P23 || P31 || P32 || P33 （3.3）

在HDL中，为了通过面积去换速度，我们将上式改变如下：

P1 = P11 || P12 || P13

P2 = P21 || P22 || P23

P3 = P31 || P32 || P33 （3.4）

P = P1 || P2 || P3

通过2个时钟/步骤的运算，便能实现腐蚀运算的结果

代码同样参考了bingo的代码

`timescale 1ns/1ns
module VIP_Bit_Dilation_Detector
#(
parameter [9:0] IMG_HDISP = 10'd640, //640*480
parameter [9:0] IMG_VDISP = 10'd480
)
(
//global clock
input clk, //cmos video pixel clock
input rst_n, //global reset
//Image data prepred to be processd
input per_frame_vsync, //Prepared Image data vsync valid signal
input per_frame_href, //Prepared Image data href vaild signal
input per_frame_clken, //Prepared Image data output/capture enable clock
input per_img_Bit, //Prepared Image Bit flag outout(1: Value, 0:inValid)
//Image data has been processd
output post_frame_vsync, //Processed Image data vsync valid signal
output post_frame_href, //Processed Image data href vaild signal
output post_frame_clken, //Processed Image data output/capture enable clock
output post_img_Bit //Processed Image Bit flag outout(1: Value, 0:inValid)
);
//----------------------------------------------------
//Generate 1Bit 3X3 Matrix for Video Image Processor.
//Image data has been processd
wire matrix_frame_vsync; //Prepared Image data vsync valid signal
wire matrix_frame_href; //Prepared Image data href vaild signal
wire matrix_frame_clken; //Prepared Image data output/capture enable clock
wire matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output
wire matrix_p21, matrix_p22, matrix_p23;
wire matrix_p31, matrix_p32, matrix_p33;
VIP_Matrix_Generate_3X3_1Bit u_VIP_Matrix_Generate_3X3_1Bit
(
//global clock
.clk (clk), //cmos video pixel clock
.rst_n (rst_n), //global reset
//Image data prepred to be processd
.per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal
.per_frame_href (per_frame_href), //Prepared Image data href vaild signal
.per_frame_clken (per_frame_clken), //Prepared Image data output/capture enable clock
.per_img_Bit (per_img_Bit), //Prepared Image brightness input
//Image data has been processd
.matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal
.matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal
.matrix_frame_clken (matrix_frame_clken), //Processed Image data output/capture enable clock
.matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output
.matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23),
.matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33)
);
//Add you arithmetic here
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//-------------------------------------------
//-------------------------------------------
//Dilation Parameter
// Original Dilation Pixel
// [ 0 0 0 ] [ 1 1 1 ] [ P1 P2 P3 ]
// [ 0 1 0 ] [ 1 1 1 ] [ P4 P5 P6 ]
// [ 0 0 0 ] [ 1 1 1 ] [ P7 P8 P9 ]
//P = P1 | P2 | P3 | P4 | P5 | P6 | P7 | 8 | 9;
//---------------------------------------
//Dilation with or operation,1 : White, 0 : Black
//Step1
reg post_img_Bit1, post_img_Bit2, post_img_Bit3;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
post_img_Bit1 <= 1'b0;
post_img_Bit2 <= 1'b0;
post_img_Bit3 <= 1'b0;
end
else
begin
post_img_Bit1 <= matrix_p11 | matrix_p12 | matrix_p13;
post_img_Bit2 <= matrix_p21 | matrix_p22 | matrix_p23;
post_img_Bit3 <= matrix_p21 | matrix_p32 | matrix_p33;
end
end
//Step 2
reg post_img_Bit4;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
post_img_Bit4 <= 1'b0;
else
post_img_Bit4 <= post_img_Bit1 | post_img_Bit2 | post_img_Bit3;
end
//------------------------------------------
//lag 2 clocks signal sync
reg [1:0] per_frame_vsync_r;
reg [1:0] per_frame_href_r;
reg [1:0] per_frame_clken_r;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
per_frame_vsync_r <= 0;
per_frame_href_r <= 0;
per_frame_clken_r <= 0;
end
else
begin
per_frame_vsync_r <= {per_frame_vsync_r[0], matrix_frame_vsync};
per_frame_href_r <= {per_frame_href_r[0], matrix_frame_href};
per_frame_clken_r <= {per_frame_clken_r[0], matrix_frame_clken};
end
end
assign post_frame_vsync = per_frame_vsync_r[1];
assign post_frame_href = per_frame_href_r[1];
assign post_frame_clken = per_frame_clken_r[1];
assign post_img_Bit = post_frame_href ? post_img_Bit4 : 1'b0;
endmodule

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