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MiniLA is a project of simple and cheap logic analyzer designed for amateur and semi-professional work.
Features:
- Up to 32 channels
- 128 Kb of memory for each channel
- Sampling rate up to 100 MHz (timebase in 1-2-5 sequence)
- External clock input
- Input levels compatible with 3.3V and 5V logic
- Selectable pretrigger/posttrigger buffer size in 8K steps
- 16 bits wide trigger (0, 1, rising/falling edge, don't care)
- Programmable min. trigger-event width (1-16)
- Programmable trigger-events counter (1-16)
- External trigger input
- Communicating via LPT port (EPP mode support) or USB
- Documentation and source codes released under GNU GPL
Hardware：
Heart of the miniLA is CPLD XC95288XL from Xilinx. This reprogrammable devices implements all of the necessary logic.
Samples are stored into fast synchronous SRAM AS7C33128.
Devices are supplied by 3.3V stabilized by LD1117DT-3.3.
Oscillator IC4(IC6) is a clock source for the CPLD. This oscillator is supplied by 3.3V. Good source for oscillators are old PC mainboards. Experiences shown, that such oscillators did not have problem to work with 3.3V power supply, although they are designed for 5V.
Project page：
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