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预览 Xilinx最新官方培训视频教程:How to use the 3 AXI Configurations,... attachment zhang1998 2021-11-17 0225 zhang1998 2021-11-17 15:24
预览 [Altium.Designer.FPGA设计指导]Altium.Designer基于FPGA嵌入式系统... attachment zhang1998 2021-11-17 0417 zhang1998 2021-11-17 15:21
预览 TSMC 0.35 标准单元库 attachment zhang1998 2021-11-17 0453 zhang1998 2021-11-17 15:20
预览 几大Foundry厂给的大量的Flash的Verilog源代码 attachment zhang1998 2021-11-17 0327 zhang1998 2021-11-17 15:14
预览 《Hardware Design Verification: Simulation and Formal Method-Based Approache... attachment zhang1998 2021-11-17 0147 zhang1998 2021-11-17 15:12
预览 《Hardware Design Verification: Simulation and Formal Method-Based Approache... attachment zhang1998 2021-11-17 0147 zhang1998 2021-11-17 15:08
预览 好东西来了!《Multi-Clock Domain data synchronization》 attachment zhang1998 2021-11-17 0145 zhang1998 2021-11-17 15:06
预览 PERL实例精解第四版中文+书签 attachment zhang1998 2021-11-17 0154 zhang1998 2021-11-17 15:04
预览 画波形图工具timegen 3.3.5破解 attachment zhang1998 2021-11-17 0446 zhang1998 2021-11-17 14:55
预览 图像信号处理器ISP和FPGA attachment zhang1998 2021-11-17 0179 zhang1998 2021-11-17 14:54
预览 Design Compiler Reference Methodology script vG-2012.06 attachment zhang1998 2021-11-17 0181 zhang1998 2021-11-17 14:47
预览 IC设计者必须会的TCL语言教程 attachment zhang1998 2021-11-17 1506 finelei2002 2021-11-17 14:26
预览 专用集成电路(中文版)(美,斯密斯著)(内含书签,... attachment zhang1998 2021-11-17 02456 zhang1998 2021-11-17 11:21
预览 夏宇闻著作:从算法设计到硬线逻辑的实现(免费!!!... attachment zhang1998 2021-11-17 0217 zhang1998 2021-11-17 11:19
预览 分享modelsim se 10.2c linux&win版+crack 百度网盘 attachment zhang1998 2021-11-17 0331 zhang1998 2021-11-17 11:16
预览 synopsys ces_sva_2006.06-SP2 lab attachment zhang1998 2021-11-17 01289 zhang1998 2021-11-17 11:14
预览 SystemVerilog Assertions Basic Tutorial attachment zhang1998 2021-11-17 0137 zhang1998 2021-11-17 11:14
预览 Cortex-M0 Tarmac 和 Verdi HWSW_Debug 使用总结 zhang1998 2021-11-17 0311 zhang1998 2021-11-17 11:11
预览 IEEE Std 1364™-2005(Verilog最新标准) zhang1998 2021-11-17 0152 zhang1998 2021-11-17 11:09
预览 完美时序Perfect Timing II book(中英文都有) attachment zhang1998 2021-11-17 0204 zhang1998 2021-11-17 11:08
预览 关于使用synopsys CoreTools 一些经验 zhang1998 2021-11-17 01550 zhang1998 2021-11-17 11:06
预览 FPGA 与 TI DSP的EMIF接口程序 attachment zhang1998 2021-11-17 0374 zhang1998 2021-11-17 11:05
预览 最经典Verilog教程《精通Verilog HDL:IC设计核心技术实例详解... attachment zhang1998 2021-11-17 1209 finelei2002 2021-11-17 11:03
预览 altium 10 crack attachment zhang1998 2021-11-17 0212 zhang1998 2021-11-17 11:03
预览 基2 8点fft verilog代码 经过modelsim仿真 attachment zhang1998 2021-11-17 0418 zhang1998 2021-11-17 11:01
预览 Systemverilog最新标准 IEEE Std 1800-2017 发布 attachment zhang1998 2021-11-17 0565 zhang1998 2021-11-17 11:00
预览 Advanced Chip Design, Practical Examples in Verilog by Mr Kishore K Mishra zhang1998 2021-11-17 03503 zhang1998 2021-11-17 10:56
预览 SystemVerilog Verification UVM 1.1 Student & Lab Guide (可搜寻 PDF) zhang1998 2021-11-17 02421 zhang1998 2021-11-17 10:55
预览 Xilinx Vivado 2018.3 License attachment zhang1998 2021-11-17 0178 zhang1998 2021-11-17 10:53
预览 Cadence公司关于设计中很重要的Timing Closure问题的介绍和解... attachment zhang1998 2021-11-17 0145 zhang1998 2021-11-17 10:50
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