TA的每日心情 | 开心 2015-10-15 14:19 |
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本帖最后由 jwl 于 2015-12-24 12:29 编辑
拿到了小脚丫的板子,写了一个IIC作为简单测试程序。给小伙伴们参考参考
好像ultraedit和帖子的代码不太兼容,有些地方比较夸张的裂开了,请忽视这些细节
发送端部分:- /*
- 数据发送端----------------------> IIC总线
- ------------------
- | |
- sclk->| |->scl
- rst->| |
- data[3:0]=>| |->sda
- | |
- ack<-| |
- ------------------
- */
- module IICsender(
- input wire sclk,
- input wire rst,
- input wire [3:0] data,
- output reg ack, //主机中断
- output reg scl,
- output reg sda
- );
-
- reg [6:0] state;
- /* reg clk, clk_inv;*/
-
- parameter
- Idle = 7'b0000001,
- Start= 7'b0000010,
- Bit4 = 7'b0000100,
- Bit3 = 7'b0001000,
- Bit2 = 7'b0010000,
- Bit1 = 7'b0100000,
- Stop = 7'b1000000;
-
- //scl信号的产生,为sclk二分频
- always @(posedge sclk)
- begin
- if (rst)
- scl <= 0;
- else
- scl <= ~scl;
- end
-
- //状态机及输出逻辑
- always @(negedge sclk) begin
- if (rst)
- begin
- sda <= 1;
- ack <= 0;
- state <= Idle;
- end
- else
- case (state)
- Idle:
- if (ack && scl) begin state<=Start; ack<=1; sda<=0;end
- else begin state<=Idle; ack<=1; sda<=1;end
- Start:
- if (ack && !scl) begin state<=Bit4; ack<=0; sda<=data[3];end
- else begin state<=Start;ack<=1;end
- Bit4:
- if (!scl) begin state<=Bit3; sda<=data[2];end
- else state<=Bit4;
- Bit3:
- if (!scl) begin state<=Bit2; sda<=data[1];end
- else state<=Bit3;
- Bit2:
- if (!scl) begin state<=Bit1; sda<=data[0];end
- else state<=Bit2;
- Bit1:
- if (!scl) begin state<=Stop; sda<=0;end
- else state<=Bit1;
- Stop:
- if (scl) begin state<=Idle; sda<=1;end
- else state<=Stop;
- endcase
- end
- endmodule
复制代码 接收端部分:- /*
- IIC总线 --------------------->数据接收端
- ------------------
- | |
- scl->| |<-rst
- | |
- | |->ack
- sda->| |->finish
- | |=>data[3:0]
- ------------------
- */
- module IICreceiver(
- input wire scl,
- input wire sda,
- input wire rst,
- output wire [3:0] data,
- output reg ack, //开始接收中断
- output reg finish //接收完成中断
- );
-
- parameter
- Idle = 6'b000001,
- Bit4 = 6'b000010,
- Bit3 = 6'b000100,
- Bit2 = 6'b001000,
- Bit1 = 6'b010000,
- Stop = 6'b100000;
- reg [5:0] state=Idle;
- reg StartFlag, StopFlag;
- reg [3:0] data_tmp;
- //开始检测电路
- always @(negedge sda)
- if (scl)
- StartFlag <= 1;
- else
- StartFlag <= 0;
- //结束检测电路
- always @(posedge sda)
- if (scl)
- StopFlag <= 1;
- else
- StopFlag <= 0;
- //状态机迁移
- always @(posedge scl)
- if (rst)
- begin
- ack <= 0;
- finish <= 0;
- state<= Idle;
- data_tmp <= 4'bzzzz;
- end
- else
- case (state)
- Idle:
- if (StartFlag) begin state<=Bit4;data_tmp[3]<=sda;ack<=1;end
- else state<=Idle;
- Bit4:
- if (ack) begin state<=Bit3;data_tmp[2]<=sda;ack<=0;end
- else state<=Bit4;
- Bit3:
- begin state<=Bit2;data_tmp[1]<=sda;end
- Bit2:
- begin state<=Bit1;data_tmp[0]<=sda;finish<=1;end
- Bit1:
- if (StopFlag) begin state<= Idle;finish<=0;end
- else state<=Bit1;
- endcase
-
- assign data = finish? data_tmp:4'bzzzz;
- endmodule
复制代码 顶层测试模块
- module IIC_top(
- input wire clk,
- input wire rst,
- input wire [3:0] send,
- output wire [3:0] receive,
- output wire receiveInt, //开始接收中断
- output wire finish //接收完成中断
- );
- wire sendInt,scl,sda;
- IICsender U1( .sclk(clk), .rst(rst),.data(send),.ack(sendInt),.scl(scl),.sda(sda));
- IICreceiver U2(.scl(scl), .sda(sda),.rst(rst),.data(receive),.ack(receiveInt),.finish(finish));
- endmodule
复制代码 |
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